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Problem in measurement of Doherty Power amplifier using Cree's CGH40010F

Power_Ani

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I have come across a problem while measuring a Doherty power amplifier, designed with CGH40010F transistors. I have biased the transistors and checked them properly before moving towards the RF analysis. The RF analysis was having a problem as it was not showing the desired gain. After that when I turn off all the setup sequentially and then check the transistor using a digital multimeter I found that the gate to source and gate to drain was showing 50 ohms which should be open load in DC condition. If I turn on the setup again for DC analysis then I found out that the drain current of the class AB carrier amplifier is flowing without the control of the gate voltage. Therefore I want to consult with you that what may be the problem with this kind of behavior.
 

vfone

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CGH40010F is a GaN power transistor which requires specific bias seuence, otherwise the transistor dies instantaneus:

- To turn-ON the device, the sequence is:
1. Apply Gate voltage (pinch-off voltage),
2. Apply Drain voltage (operating voltage),
3. Adjust Gate voltage (adjust to set operating/quiescent current),
4. Turn RF signal ON.

- To turn-OFF the device, the sequence is reversed:
1. Turn RF signal OFF,
2. Adjust Gate voltage (adjust to pinch-off voltage),
3. Adjust Drain voltage (reduces to zero volts then turn-off),
4. Turn-off Gate voltage (wait 2 seconds and then turn-off).

GaN dead transistors behave different when measured with a digital multi-meter.
 

Power_Ani

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CGH40010F is a GaN power transistor which requires specific bias seuence, otherwise the transistor dies instantaneus:

- To turn-ON the device, the sequence is:
1. Apply Gate voltage (pinch-off voltage),
2. Apply Drain voltage (operating voltage),
3. Adjust Gate voltage (adjust to set operating/quiescent current),
4. Turn RF signal ON.

- To turn-OFF the device, the sequence is reversed:
1. Turn RF signal OFF,
2. Adjust Gate voltage (adjust to pinch-off voltage),
3. Adjust Drain voltage (reduces to zero volts then turn-off),
4. Turn-off Gate voltage (wait 2 seconds and then turn-off).

GaN dead transistors behave different when measured with a digital multi-meter.
Yes, I have done exactly the same procedure as you have mentioned. I think I could not clearly mention the exact problem that I'm facing while measuring the DPA. I have designed a single class AB driver amplifier with the same transistor and it is working fine. While connecting the two transistors in a Doherty configuration it shows absolutely fine in the DC bias testing. But after applying the RF signal the problem occurs. After removing the RF signal if I again go for the DC testing then the class AB carrier amplifier is showing some abnormalities, like Schottky junction breakdown. I am trying to figure out why it is happening. What may be the source of this abnormality? The peaking amplifier, biased in class C, is absolutely working fine.
 

vfone

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Assuming that the carrier class-AB transistor is still alive, the gate voltages of the carrier and peak amplifiers (for CGH40010F transistors) should be biased at: -2.8V for Class-AB, and -4.2V for Class-C, when both drain voltages are biased at +28V.
The gain of the carrier (AB) amplifier is higher than the gain of the peak amplifier (C), so it will make it more capable for oscillations, which needs to be verified.
 

Power_Ani

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Assuming that the carrier class-AB transistor is still alive, the gate voltages of the carrier and peak amplifiers (for CGH40010F transistors) should be biased at: -2.8V for Class-AB, and -4.2V for Class-C, when both drain voltages are biased at +28V.
The gain of the carrier (AB) amplifier is higher than the gain of the peak amplifier (C), so it will make it more capable for oscillations, which needs to be verified.
Yes, I have biased the class AB at -2.73V and class C at -4.5V. Drain voltages were kept at 28V. I have also verified the oscillation condition in simulation which is showing absolutely fine. But how can I verify that in measurement for which the class AB amplifier is getting damaged?
 

vfone

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To test for oscillations, use a spectrum analyzer at the output of the PA. Beware that most of the spectrum analyzers have a max input level of 1W (30dBm), so have to place the necessary attenuators between PA and the analyzer.
Check for oscillations for higher frequency range than your PA bandwidth.

To improve PA stability use for gate and drain bias decoupling, the capacitors recommended on page 9 of the datasheet (C4 to C8 and C12 to C17), and for gate stability use the gate RC network recommended here in fig.10:

 

BigBoss

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Power Amplifiers are very easily destroyed by any means due to High Voltage and High Current.
Even-tough such transistors have been designed against high mismatch effect, there is still dangers for such RF Power Transistors. While designing an PA, you have to be sure that every Matching Circuit has been carefully designed and implemented. After that, you must measure every fine point of the layout otherwise small amount of mismatch or a high tolerance capacitor or inductor or a layout discrepancy will blow or destroy your active devices. You should go step by step. Don't apply supplies when it's been done, instead measure every matching circuit, stubs, transmission lines etc. then compare them to simulated ones.
RF Power transistors are expensive guys..
 

Power_Ani

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Power Amplifiers are very easily destroyed by any means due to High Voltage and High Current.
Even-tough such transistors have been designed against high mismatch effect, there is still dangers for such RF Power Transistors. While designing an PA, you have to be sure that every Matching Circuit has been carefully designed and implemented. After that, you must measure every fine point of the layout otherwise small amount of mismatch or a high tolerance capacitor or inductor or a layout discrepancy will blow or destroy your active devices. You should go step by step. Don't apply supplies when it's been done, instead measure every matching circuit, stubs, transmission lines etc. then compare them to simulated ones.
RF Power transistors are expensive guys..
Yes. That's true. We can verify the reflections at different nodes in simulation but how do we measure that when the circuit is fabricated? Without giving bias voltages we cannot measure the terminal S parameters. In my circuit, I haven't used any inductors but I have capacitors from ATC 600S series in the RF line. In simulations, I have used the s2p files of every SMD capacitor and the co-simulation of the full layout is showing good results. The self-resonance frequency of the capacitor lies beyond the design frequency of the amplifier.
--- Updated ---

To test for oscillations, use a spectrum analyzer at the output of the PA. Beware that most of the spectrum analyzers have a max input level of 1W (30dBm), so have to place the necessary attenuators between PA and the analyzer.
Check for oscillations for higher frequency range than your PA bandwidth.

To improve PA stability use for gate and drain bias decoupling, the capacitors recommended on page 9 of the datasheet (C4 to C8 and C12 to C17), and for gate stability use the gate RC network recommended here in fig.10:

Thanks. I will check the whole frequency range of the spectrum analyzer in the next measurement. The stability arrangements are already made in the circuit and verified the unconditional stability in simulation for 3 times the design frequency range. It was showing stable for the whole range.
 

G4BCH

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how do we measure that when the circuit is fabricated?

Before fitting the device, terminate the input and output and then measure the impedances the device will see. It may be tricky to do and not very accurate, but will at least tell you that you are close to what you want.

Thanks. I will check the whole frequency range of the spectrum analyzer in the next measurement. The stability arrangements are already made in the circuit and verified the unconditional stability in simulation for 3 times the design frequency range. It was showing stable for the whole range.

Check for stability at low frequencies too. Poor decoupling of the power supplies at LF can cause instability that will destroy a PA just as easily, if not more so, as instability at the operating frequency.
 

Power_Ani

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Before fitting the device, terminate the input and output and then measure the impedances the device will see. It may be tricky to do and not very accurate, but will at least tell you that you are close to what you want.



Check for stability at low frequencies too. Poor decoupling of the power supplies at LF can cause instability that will destroy a PA just as easily, if not more so, as instability at the operating frequency.
Yes, I have checked the stability for DC - 3fo range where fo is the design frequency and it is unconditionally stable. In my circuit, two amplifiers are parallel connected in a Doherty manner. These amplifiers were designed separately and then combined using a load combiner. Therefore if I try to measure the input impedance according to your procedure then I will not see any nearby impedance values which may be misleading. That's why I want to know if this is the right way to measure things or I need to adapt another way.
One more thing I want to ask is that as one of the transistors is burnt and if I have to measure the amplifier with a new transistor on board it may also get damaged in the same way. Then what precautions need to be taken before measuring the amplifier?
 

G4BCH

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For the impedance measurement I would simulate the matching structure with the stage you are not measuring open circuit. that is 4 simulations and 4 measurements. It is just to check that the matching structure is something close to what you expect. The devices are out of circuit for the measurements obviously.

As for powering up the amplifier, I would apply the gate bias and check that all is well (you probably have done this before anyway but it does not hurt to check again) then using a current limited supply slowly increase the drain voltage while watching the current and spectrum analyser display. I would have the current limit set quite low to start and also set the class B stage bias to keep the standing current to around the limit set on the PSU. If all is well then slowly increase the current limit and standing current again watching the analyser.

Another thought on LF stability, is the power supply stable with whatever load the amplifier is presenting to it, it has not happened to me, but a colleague had a SMPSU oscillate and do some damage with over voltage. Probably not a cause here, but make sure that high levels of RF are kept out of the PSU that can create havoc too.
 

Power_Ani

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For the impedance measurement I would simulate the matching structure with the stage you are not measuring open circuit. that is 4 simulations and 4 measurements. It is just to check that the matching structure is something close to what you expect. The devices are out of circuit for the measurements obviously.

As for powering up the amplifier, I would apply the gate bias and check that all is well (you probably have done this before anyway but it does not hurt to check again) then using a current limited supply slowly increase the drain voltage while watching the current and spectrum analyser display. I would have the current limit set quite low to start and also set the class B stage bias to keep the standing current to around the limit set on the PSU. If all is well then slowly increase the current limit and standing current again watching the analyser.

Another thought on LF stability, is the power supply stable with whatever load the amplifier is presenting to it, it has not happened to me, but a colleague had a SMPSU oscillate and do some damage with over voltage. Probably not a cause here, but make sure that high levels of RF are kept out of the PSU that can create havoc too.
I have verified the circuit again. I found out that it is a problem with DC. I have set the gate voltages for both the class AB and C amplifiers below the cutoff voltage and then turned on the drain bias voltage for both the amplifiers. Then I increased the drain bias voltage for both the amplifiers to the rated voltage of 28V. After that when I tried to increase the gate bias voltage of the class AB amplifier it is showing that the drain current is flowing despite being the gate voltage below cut-off and it is showing lost gate control. The current limiter was set to 300 mA. I have checked the DCIV characteristics of both the amplifiers twice separately and it was showing fine. Can you please tell me what should I do in this scenario? I am really clueless about this.
 

amihomo

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As other gurus mentioned above for GaN devices you should follow the bias sequence as specified in the app notes.

Never apply the drain before the gate bias is settled.

As a general rule, you should apply a negative voltage to the gate making sure that the transistor is off.
Then apply the rated Drain Voltage. After that gently increase the gate bias voltage and watch the drain current increasing to the required value for the PA class.

Placing RC filters at gate and drain helps suppressing the video oscillation.
 

generator3838

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Assuming that the carrier class-AB transistor is still alive, the gate voltages of the carrier and peak amplifiers (for CGH40010F transistors) should be biased at: -2.8V for Class-AB, and -4.2V for Class-C, when both drain voltages are biased at +28V.
The gain of the carrier (AB) amplifier is higher than the gain of the peak amplifier (C), so it will make it more capable for oscillations, which needs to be verified.
Yes, I have biased the class AB at -2.73V and class C at -4.5V. Drain voltages were kept at 28V. I have also verified the oscillation condition in simulation which is showing absolutely fine. But how can I verify that in measurement for which the class AB amplifier is getting damaged?
Hi, can you please tell how you measured -2.8 for class-AB and -4.2 for class-C? Also, can you please tell how to find Q-point of amplifier to operate in Class-AB or Class-C?
 

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