sdmcet
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hi,friends i m doing project on ldpc generator matrix encoder c=G*u but getting error as"and cannot have such operands in this context plz help me.
following is my code:
following is my code:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bn is Port ( u : in std_logic_vector(3 downto 0); clk:in std_logic; c : out std_logic_vector(7 downto 0)); end bn; architecture Behavioral of bn is type hmatrix is array (0 to 3 ) of std_logic_vector(7 downto 0); constant G:hmatrix:=("10001100", "01001001", "00100011", "00010110"); begin process(clk) begin if(clk'event and clk='1') then c(7)<=(u(3) and G(31)) or (u(2) and G(23)) or (u(1) and G(15)) or (u(0) and G(7)); c(6)<=(u(3) and G(30)) or (u(2) and G(22)) or (u(1) and G(14)) or (u(0) and G(6)); c(5)<=(u(3) and G(29)) or (u(2) and G(21)) or (u(1) and G(13)) or (u(0) and G(5)); c(4)<=(u(3) and G(28)) or (u(2) and G(20)) or (u(1) and G(12)) or (u(0) and G(4)); c(3)<=(u(3) and G(27)) or (u(2) and G(19)) or (u(1) and G(11)) or (u(0) and G(3)); c(2)<=(u(3) and G(26)) or (u(2) and G(18)) or (u(1) and G(10)) or (u(0) and G(2)); c(1)<=(u(3) and G(25)) or (u(2) and G(17)) or (u(1) and G(9)) or (u(0) and G(1)); c(0)<=((u(3) and G(24)) or (u(2) and G(16)) or (u(1) and G(8)) or (u(0) and G(0))); end if; end process; end Behavioral;
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