problem in getting the output

[Arindam123]

hey there,
i am trying to simulate the mod operation in modelsim and i am not getting a proper output.

my code is

entity divi is
port( a,b : in std_logic_vector(15 downto 0);
y : out std_logic_vector(15 downto 0)
);
end divi;

architecture ber of divi is

signal a1,b1,c1 : integer;
signal temp: std_logic_vector(15 downto 0);
begin
process(a,b)
begin

a1<= conv_integer(a);
b1<= conv_integer(b);
c1<= a1 mod b1;

temp <= conv_std_logic_vector(c1,16);

y<= temp;
end process;
end ber;

the values of a ab b are "0000000000001100" and"0000000000000111"

i am getting a1,b1,c1 all zeroes.

can anyone help me out where the problem is???