module top(clk,
sinit,
din,
wr_en,
dout,
full,
empty,
DATA,
addr_en,
rd_sel,
readout_en,
count_chk,
addr_in);
input clk,sinit,readout_en,addr_en;
input [31:0] din;
input [3:0] wr_en;
// just for checkin
output [1:0] rd_sel;
//////////////////
input [1:0] addr_in;
inout [31:0] DATA;
output [31:0] dout;
reg [31:0] dout;
output [3:0] empty,full;
wire [39:0] data_count;
wire [3:0] rd_en;
wire [31:0] dout1,dout2,dout3,dout4;
output [9:0] count_chk;
makeme block1(.clk(clk),.sinit(sinit),.din(din),
.wr_en(wr_en[0]),.rd_en(rd_en[0]),.dout(dout1),
.full(full[0]),.empty(empty[0]),
.data_count(data_count[9:0]));
makeme block2(.clk(clk),.sinit(sinit),.din(din),
.wr_en(wr_en[1]),.rd_en(rd_en[1]),.dout(dout2),
.full(full[1]),.empty(empty[1]),
.data_count(data_count[19:10]));
makeme block3(.clk(clk),.sinit(sinit),.din(din),
.wr_en(wr_en[2]),.rd_en(rd_en[2]),.dout(dout3),
.full(full[2]),.empty(empty[2]),
.data_count(data_count[29:20]));
makeme block4(.clk(clk),.sinit(sinit),.din(din),
.wr_en(wr_en[3]),.rd_en(rd_en[3]),.dout(dout4),
.full(full[3]),.empty(empty[3]),
.data_count(data_count[39:30]));
assign count_chk=data_count[29:20];
reg [31:0] data_bus;
//assign DATA[1:0]=(addr_en)?addr_in
(readout_en)?2'b00:data_bus[1:0]);
assign DATA[1:0]=(addr_en)?addr_in:data_bus[1:0];
//assign DATA[1:0]=(addr_en)?2'bz:data_bus[1:0];
assign DATA[31:2]=readout_en?30'b0:data_bus[31:2];
//assign DATA[31:2]=addr_en?30'b0:32'bz;
//assign DATA=((addr_en==1'b0)&(readout_en==1'b0))?data_bus:32'bz;
//assign DATA=readout_en?32'bz:32'bz;
//assign DATA=data_bus;
reg [1:0] rd_sel;
always@(posedge clk)
begin
if(addr_en)
rd_sel<=DATA[1:0];
end
assign rd_en=(readout_en)?(rd_sel[1]?(rd_sel[0]?4'b1000:4'b0100)
rd_sel[0]?4'b0010:4'b0001)):4'b0000;
//assign rd_en=(readout_en)?(rd_sel[1]?(rd_sel[0]?((data_count[9:0]>10'b0000110010)? 4'b1000:4'b0000):4'b0100)
rd_sel[0]?4'b0010:4'b0001)):4'b0000;
wire [31:0] mux_out;
assign mux_out=rd_sel[1]?(rd_sel[0]?dout4:dout3)
rd_sel[0]?dout2:dout1);
always@(negedge clk)
begin
data_bus<=mux_out;
dout<=DATA;
end
endmodule
////////////////////////////////////////////////////////////////////
The above is my complete code.....