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problem in address maping for MC and cpld

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majidshahpouri

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hello every body
I have a problam .my problem is that I want to use MC196 and one xc9572. I want to have a address mapping and can read and write to databus I write this code.when I used the line Dgtout<=(others=>'Z') my cpld work but this output dont work .but when idont use this code cpld dont work.what shoud I do that Icanddress and can read and write to them.
Code:
entity test2 is
port (
RD: in std_logic;
WR: in std_logic;
ALE: in std_logic ;
D: inout std_logic_vector (1 to 8):="ZZZZZZZZ"; --ADDRESS AND DATA D[0:7]
ADD: in std_logic_vector (1 to 8); -- ADDRESS A8 TO A15
STU :eek:ut std_logic;
adl :eek:ut std_logic;
DGTOUT : out std_logic_vector (1 to 8); -- out put demanding
DGTOUT1 : out std_logic_vector (1 to 8); -- out put demanding
A: out std_logic_vector (1 to 8); -- ADDRESS A[0:15]
LED: out std_logic_vector ( 1 to 2 )

);
end test2;

architecture test2_arch of test2 is
signal led_select: bit;
signal in_select: bit;
signal out_select: bit;
signal out_select1: bit;
signal busin:std_logic_vector (1 to 8);
signal busout:std_logic_vector(1 to 8);
begin
busin<=D;
--mapping process
process(add,RD,WR)
begin
if ( ( ADD(8) and ADD(7) and (not ADD(6)) and (not ADD(5)) and (not ADD(4))and ( ADD(3)) and (not ADD(2)) and ( ADD(1)) and ( (not RD) or (not WR ) )) ) = '1' then --add D000
out_select <='1';
else
out_select<='0' ;
end if;
if ( ( ADD(8) and ADD(7) and (not ADD(6)) and (not ADD(5)) and (not ADD(4))and (not ADD(3)) and (not ADD(2)) and (not ADD(1)) and ( (not RD) or (not WR ) )) ) = '1' then --add c000
out_select1 <='1';
else
out_select1<='0' ;
end if;
if ( ( ADD(8) and ADD(7) and ADD(6) and (not ADD(5)) and (not ADD(4))and (not ADD(3))and (not ADD(2))and (not ADD(1)) and((not RD)or(not WR ))) )= '1' then --add E000
led_select<='1';
else
led_select<='0' ;
end if;
if ( ( ADD(8) and (not ADD(7)) and ADD(6) and ADD(5) and (not ADD(4))and (not ADD(3))and (not ADD(2))and (not ADD(1)) and ((not RD) or (not WR )) )) = '1' then--add
in_select <='1';
else
in_select<='0' ;
end if;
end process;

------***************************************************************************
-- address select
PROCESS(add,ALE,led_select,rd,wr,out_select,D,in_select,out_select1)
variable out_data1 : STD_LOGIC_vector(1 to 8);
variable out_data : STD_LOGIC_vector(1 to 8);
variable in_data : STD_LOGIC_vector(1 to 8);
begin

if out_select1 ='1' then

for i in 1 to 8 loop
out_data1(i) := busin( i );
end loop;
end if;
if out_select1 ='1' then
DGTOUT1<= out_data1;
end if;
if out_select ='1' then

for i in 1 to 8 loop
out_data1(i) := D( i );
end loop;
end if;
if out_select1 ='1' then
DGTOUT1<= out_data1;
e3se
DGTOUT1<= others='Z'
end if;

--========================================
if led_select = '1' then
for i in 1 to 2 loop
LED ( i ) <= D ( i+2 ) ;
end loop;
end if;

end process;
PROCESS(ALE,D)
begin
if ALE= '1' then --ale rising edge
for i in 1 to 8 loop
A(i)<=D(i);
end loop;
end if;
end process;



end test2_arch;
 

EDALIST

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i think this is a wierd code.

it should be re-write.
 

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