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| -- Four-bits divider
library IEEE;
use IEEE.std_logic_1164.all;
entity Divider_nBits is
generic(N : integer :=4);
port ( divisor : in std_logic_vector(N-1 downto 0); -- divisor
dividend : in std_logic_vector(2*N-2 downto 0); -- dividend
remainder : out std_logic_vector(N-1 downto 0); -- remainder
quotient : out std_logic_vector(N-1 downto 0) -- quotient
);
end entity ;
---------------------- Architecture Section ----------------------------------
architecture Stractural of Divider_nBits is
--------------- Signal Declarations for instantiate
type c_array is array (0 to N-1) of std_logic_vector(0 downto N) ;
type r_array is array (0 to N-1) of std_logic_vector(0 downto N-1);
signal sig_r : r_array ;
signal sig_c : c_array ;
begin
-- Instantiate N single-bit controlled add/subtract
LGEN: for i in 0 to N-1 generate
LGEN2: for j in 0 to N-1 generate
First_column:if j=0 and i/=N-1 generate
CAS_i3:entity work.CAS(ADD_SUB) -- First Column
port map ( divisor => divisor(j) ,
reminder_in => dividend(j) ,
T => not sig_r(i+1)(N-1) ,
cin => sig_c(i)(j) ,
reminder_out => sig_r(i)(j) ,
cout => sig_c(i)(j+1) );
end generate;
Last_stage: if i=N-1 and j/=0 generate -- Last row
CAS_ij:entity work.CAS(ADD_SUB)
port map ( divisor => divisor(j) ,
reminder_in => dividend(j+N-1) ,
T => '1' ,
cin => sig_c(i)(j) ,
reminder_out => sig_r(i)(j) ,
cout => sig_c(i)(j+1) );
end generate;
other_stage: if i/=N-1 and j/=0 generate -- others
CAS_i2:entity work.CAS(ADD_SUB)
port map ( divisor => divisor(j) ,
reminder_in => sig_r(i+1)(j-1) ,
T => not sig_r(i+1)(N-1) ,
cin => sig_c(i)(j) ,
reminder_out => sig_r(i)(j) ,
cout => sig_c(i)(j+1) );
end generate;
end generate;
end generate;
end ; |