problem in access one bit of array

[digital design]

Hi every body
I have bellow code:

---

Code VHDL - [expand]
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-- Four-bits divider
library IEEE;
use IEEE.std_logic_1164.all;
 
entity Divider_nBits is
    generic(N : integer :=4);
    port ( divisor   : in  std_logic_vector(N-1 downto 0);     -- divisor
           dividend  : in  std_logic_vector(2*N-2 downto 0);   -- dividend
           remainder : out std_logic_vector(N-1 downto 0);     -- remainder
           quotient  : out std_logic_vector(N-1 downto 0)      -- quotient
         );
end entity ;
 
---------------------- Architecture Section ----------------------------------
 
architecture Stractural of Divider_nBits is
--------------- Signal Declarations for instantiate
 
type   c_array   is array (0 to N-1)  of std_logic_vector(0 downto N)  ;
type   r_array   is array (0 to N-1)  of std_logic_vector(0 downto N-1);
 
signal sig_r : r_array ;
signal sig_c : c_array ;
 
begin
 
  
-- Instantiate N single-bit controlled add/subtract
    LGEN: for i in 0 to N-1 generate
     LGEN2:     for j in 0 to N-1 generate
      First_column:if j=0 and i/=N-1 generate   
       CAS_i3:entity work.CAS(ADD_SUB)           -- First Column
       port map ( divisor       => divisor(j)           ,
                  reminder_in   => dividend(j)          ,
                  T             => not sig_r(i+1)(N-1)  , 
                  cin           => sig_c(i)(j)          ,
                  reminder_out  => sig_r(i)(j)          ,
                  cout          => sig_c(i)(j+1)       );
       end generate;
      Last_stage: if i=N-1 and j/=0 generate     -- Last row
       CAS_ij:entity work.CAS(ADD_SUB)
       port map ( divisor       => divisor(j)      ,
                  reminder_in   => dividend(j+N-1) ,
                  T             => '1'             ,
                  cin           => sig_c(i)(j)     ,
                  reminder_out  => sig_r(i)(j)     ,
                  cout          => sig_c(i)(j+1)  );
       end generate;
      other_stage: if i/=N-1 and j/=0 generate    -- others
       CAS_i2:entity work.CAS(ADD_SUB)
       port map ( divisor       => divisor(j)          ,
                  reminder_in   => sig_r(i+1)(j-1)     ,
                  T             => not sig_r(i+1)(N-1) ,
                  cin           => sig_c(i)(j)         ,
                  reminder_out  => sig_r(i)(j)         ,
                  cout          => sig_c(i)(j+1)      );
       end generate;
  
     end generate;           
    end generate;
 
 
end ;

---

I have bellow errors in synthesize:

ERROR:HDLCompiler:1315 - Line 38: Index value <3> is out of range [0:3]
ERROR:HDLCompiler:1315 - Line 39: Index value <0> is out of range [0:4]
ERROR:HDLCompiler:1315 - Line 40: Index value <0> is out of range [0:3]
ERROR:HDLCompiler:1315 - Line 41: Index value <1> is out of range [0:4]

first error is about this line of code :

                 T             => not sig_r(i+1)(N-1)  , 
N-1 = 3 
type   r_array   is array (0 to N-1)  of std_logic_vector(0 downto N-1);
signal sig_r : r_array ;

3 is in range but I can't find out reason of errors..!!
please help me....

 

[andre_luis]

Taking a brief look at the code, in line...

T             => not sig_r(i+1)(N-1)  ,

...It looks like the index i inside the for loop is attempting to access the sig_r variable beyond the magnitude of 3 bits, that was declared at the line...

type   r_array   is array (0 to N-1)  of std_logic_vector(0 downto N-1);

 

[digital design]

Sorry, I can't find out your mean...
Do you mean my code is false ?

 

[TrickyDicky]

At line 35, (i+1) goes outside the bounds of the array when i = N-1

 

[vGoodtimes]

"0 downto N-1" might also be an error.

 

[TrickyDicky]

"0 downto N-1" might also be an error.

Oh yeah - not a VHDL error - user error.

 

[vGoodtimes]

ah, ok. This might be the issue. From what I can tell, that results in a 0 length vector. Any indexing fails. I suspect the code for reporting the error is shared between VHDL and Verilog, so it reports something that looks like a valid type.

 

[TrickyDicky]

ah, ok. This might be the issue. From what I can tell, that results in a 0 length vector. Any indexing fails. I suspect the code for reporting the error is shared between VHDL and Verilog, so it reports something that looks like a valid type.

Certainly looks that way
Im pretty sure with Quartus is warns you about a null array and gives a more useful error message.

 

[digital design]

"0 downto N-1" might also be an error.

yes, exactly ...
It is my error.
Many thanks.