problem having fixed.pkg in VHDL

[nick123]

hello,everyone..i dont know much about this site,i just joined today and the reason for joining is i m having problem in using "fixed.pkg" of VHDL.I am writing a code of radix-4,16-point fft,whole code is ready but i m stucked in one place.

Its two's complement code:

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all;
 
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.all;
------------------------------------------------
entity twoscompliment is
 
 generic (width:natural:=32);
   port(
        A              : in sfixed (8 downto -7);
        compliment : out sfixed (8 downto -7)
        );
 
end twoscompliment;
----------------------------------------------------
architecture behav of twoscompliment is
 
    signal result1 : sfixed (9 downto -7); 
    signal result2 : sfixed (9 downto -7); 
   
 begin
     result1     <= -(A);
     result2     <= to_sfixed(result1,9,-7);
    
    ----result2:=resize(result1,result2'high,result2'low,fixed_wrap,fixed_truncate); 
   
     
      compliment  <= result2 (9 downto -6) ; ------truncat1ng last 1-bit 
 
end behav;

---

problem is in the line -result1<= -(A);
result2<= to_sfixed(result1,9,-7);

if i use the comment line----result2:=resize(result1,result2'high,result2'low,fixed_wrap,fixed_truncate);

problem is still there,IS THERE ANYONE WHO CAN HELP ME,
THANK YOU IN ADVANCE.

 

[FvM]

You didn't tell what's the problem is.

 

[nick123]

You didn't tell what's the problem is.

the problem is with the to_sfixed function i used in line '' result2<= to_sfixed(result1,9,-7); ''Am I using it correctly?
Is this code correct or not? i want two's complement code of fixed type input,
I USED DAVIS BOSHOP'S " Fixed_pkg_c.vhdl "