it would be a lot easier if u can post a pic of ur test bench.
may be , setting up initial conditions at important nodes such as the output of charge pump might help. Do u have individual verilog blocks for each element in the PLL or the whole PLL as such?
another suggestion would be to check the disk space. the transient analysis stores info in the psf folder in simulation directory, running for 2 us might create a big file, if that is the case, u might wanna select only the output nodes u r interested in, by using outputs -> save all option and selecting ' selected ' for ' select signals to output(save)' and select the signals u wish to plot using outputs -> to be plotted.