problem about Synthesis

[blue1988]

hi all，
our design has 4 clock port，how can i constraint my design about the clock during Synthesis？i always meet hold time violation because i can't set the suitable
timing constrain.anyone has a manual about it?pleas attach it or give a link,thanks.
regards

 

[rca]

I expect you have define 4 create_clock?
At the synthesis step only, the hold time does not need to be check, only the setup is manage by the synthesis phase.
Only after the hold time fixing step, the hold time must be check.

 

[blue1988]

rca,
thanks for your raplay.
regards

 

[salma ali bakr]

you should constrain your design according to its surrounding environment...so you should see where your inputs are coming from and where your outputs are going to be able to constrain your ports...this includes the clock signals and their uncertainty