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problem about pipelined adc

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lhlbluesky

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for a 10 bit 1.5 bit per stage pipelied adc,how to simulate the transfer characteristic curve vout~vin?
someone says using a ramp input can be ok,but ramp is tran signal,then how to get the curve of vout~vin?
besides,how to simualte the noise of pipelined adc?and what's the range of noise value?in the order of several uV?
 

dineshbabumm

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Give a slow varying ramp input to your MDAC block.. You must get a residue plot as shown in this figure.. This one is for one block.. You cascade many such blocks.. The frequencey of the residue(i mean the periodicity) increases with the stages..



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To simulate the noise, we used the noise analysis available in Cadence.. It must be in few uV usually.. The noise floor is set by assuming the quantization noise dominates over the thermal noise(KT/C noise)..
 

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