problem about LDO design-change of ESR changes pole

[flying591]

problem about LDO!

hi everyone

In a LDO circuit, I change the value of the ESR resistance, it should only change the zero which is generated by Resr.but at some values it not only change the zero bu also change the pole. moreover,the changed pole has imaginary part.
why??
for this pole,how compensation?
thanks in advance for any response that may help me!

 

[LvW]

Re: problem about LDO!

hi everyone

In a LDO circuit, I change the value of the ESR resistance, it should only change the zero which is generated by Resr.but at some values it not only change the zero bu also change the pole. moreover,the changed pole has imaginary part.
why??
for this pole,how compensation?
thanks in advance for any response that may help me!

If the load resistance RL across the series connection Resr-Cs is rather low, there is a (slight) influence of Resr also on the pole location beause the sum Resr+RL determines the pole frequency. This can be seen and calculated by a simple equivalent circuitry. Why do you want to compensate this pole ? Do you know the motivation for the output capacitance Cs ?

 

[flying591]

Re: problem about LDO!

hi everyone

In a LDO circuit, I change the value of the ESR resistance, it should only change the zero which is generated by Resr.but at some values it not only change the zero bu also change the pole. moreover,the changed pole has imaginary part.
why??
for this pole,how compensation?
thanks in advance for any response that may help me!

If the load resistance RL across the series connection Resr-Cs is rather low, there is a (slight) influence of Resr also on the pole location beause the sum Resr+RL determines the pole frequency. This can be seen and calculated by a simple equivalent circuitry. Why do you want to compensate this pole ? Do you know the motivation for the output capacitance Cs ?

Sorry! the problem I said is not clearly!
Specifically! when Resr=0.1 simulation result
****** pole/zero analysis tnom= 25.000 temp= 25.000
******

input = 0:v_v3 output = v(111


input = 0:v_v3 output = v(111

poles (rad/sec) poles ( hertz)
**********************************************************************
real imag real imag
-487.7838k -864.8038k -77.6332k -137.6378k
-487.7838k 864.8038k -77.6332k 137.6378k
-10.6519x 0. -1.6953x 0.
-250.3852x 0. -39.8500x 0.
-368.1041x -161.1716x -58.5856x -25.6513x
-368.1041x 161.1716x -58.5856x 25.6513x
-399.9232x 0. -63.6498x 0.
zeros (rad/sec) zeros ( hertz)
**********************************************************************
real imag real imag
-1.0000x 0. -159.1549k 0.
-248.8822x 0. -39.6108x 0.
-365.5345x 251.9861x -58.1766x 40.1048x
-365.5345x -251.9861x -58.1766x -40.1048x
1.4730g 1.7979g 234.4380x 286.1465x
1.4730g -1.7979g 234.4380x -286.1465x
-3.1062g 0. -494.3622x 0.
when Resr=0.2
poles (rad/sec) poles ( hertz)
**********************************************************************
real imag real imag
-791.1464k 0. -125.9149k 0.
-1.4024x 0. -223.2004k 0.
-9.3955x 0. -1.4953x 0.
-250.3834x 0. -39.8498x 0.
-368.0945x -161.1854x -58.5841x -25.6535x
-368.0945x 161.1854x -58.5841x 25.6535x
-399.9812x 0. -63.6590x 0.
zeros (rad/sec) zeros ( hertz)
**********************************************************************
real imag real imag
-500.0000k 0. -79.5775k 0.
-248.8822x 0. -39.6108x 0.
-365.5345x 251.9861x -58.1766x 40.1048x
-365.5345x -251.9861x -58.1766x -40.1048x
1.4730g 1.7979g 234.4380x 286.1465x
1.4730g -1.7979g 234.4380x -286.1465x
-3.1062g 0. -494.3622x 0.
when Resr=0.3

poles (rad/sec) poles ( hertz)
**********************************************************************
real imag real imag
-373.0597k 0. -59.3743k 0.
-3.7192x 0. -591.9233k 0.
-7.4589x 0. -1.1871x 0.
-250.3816x 0. -39.8495x 0.
-368.0851x -161.1990x -58.5826x -25.6556x
-368.0851x 161.1990x -58.5826x 25.6556x
-400.0383x 0. -63.6681x 0.
-925.4669g 0. -147.2926g 0.
zeros (rad/sec) zeros ( hertz)
**********************************************************************
real imag real imag
-333.3333k 0. -53.0516k 0.
-248.8822x 0. -39.6108x 0.
-365.5345x 251.9861x -58.1766x 40.1048x
-365.5345x -251.9861x -58.1766x -40.1048x
1.4730g 1.7979g 234.4380x 286.1465x
1.4730g -1.7979g 234.4380x -286.1465x
-3.1062g 0. -494.3622x 0.

I do not know why, is that my simulation method wrong?
the command of HSPICE is .pz v(111) v_v3

 

[LvW]

Re: problem about LDO!

Hi flying591,

Unfortunately, I am not familiar with HSPICE and its p-z analysis.
But I think, the picture resp. your problem is not clear by using this analysis since all poles and zeros of the whole circuitry are shown - even all non-dominant values originated by the transistors.
What about a simple ac analysis showing the real frequency response and the effect of dominant poles and zeros ? I hope the situation then will be much clearer.
Regards

 

[flying591]

Re: problem about LDO!

Hi flying591,

Unfortunately, I am not familiar with HSPICE and its p-z analysis.
But I think, the picture resp. your problem is not clear by using this analysis since all poles and zeros of the whole circuitry are shown - even all non-dominant values originated by the transistors.
What about a simple ac analysis showing the real frequency response and the effect of dominant poles and zeros ? I hope the situation then will be much clearer.
Regards

Thanks for your advice!
by the way, I want to simulate the phase margin of LDO, can I simulate the circuit as shown in circuit diagram ?

 

[LvW]

Re: problem about LDO!

by the way, I want to simulate the phase margin of LDO, can I simulate the circuit as shown in circuit diagram ?

Yes, I think so. The loop gain in this case is simply the ratio V(1)/V(2).

 

[sachinagg77]

Re: problem about LDO!

Flying

I saw your circuit. I think you will have serious problem in securing enough phase margin with this circuit for all corners. You have three high gain stages...each will generate a pole.

The external capacitor in your simulation is 10u but it might change by as much as +/- 50% due to temperature. Please check for the variations in its value.

Further, you need a model for the IO/PIN parasitics whcih might have a big influence on stability and circuit performance.

Wishing you good luck

Sachin

 

[rock_zhu]

problem about LDO!

make use of one stage amp U will get a stable LDO