slchen
Member level 2
Dear all:
I am designing a 32k crystal oscillator.
And I have done the AC simulation to ensure the loop phase and loop gain!
The followed figures are the schmatic and the simulation results.
Please see the picture of the simulation results.
We can see there are two operation points A and B when phase=0.
At point A, the loop gain is larger than 1.
At point B, the loop gain is smaller than 1.
Are this results correct?
If yes, how do I ensure that the operation point of the crystal osc. is at A (not at B) in real chip.
Sincerely,
slchen
I am designing a 32k crystal oscillator.
And I have done the AC simulation to ensure the loop phase and loop gain!
The followed figures are the schmatic and the simulation results.
Please see the picture of the simulation results.
We can see there are two operation points A and B when phase=0.
At point A, the loop gain is larger than 1.
At point B, the loop gain is smaller than 1.
Are this results correct?
If yes, how do I ensure that the operation point of the crystal osc. is at A (not at B) in real chip.
Sincerely,
slchen