Priority keyword of System Verilog

[fragnen]

Do the priority keyword of System Verilog make an incomplete case statement behave as a full case?

 

[dave_59]

The priority and unique keywords before a SystemVerilog case statement do not change the execution behavior of the case statement. However, they do provide violation errors if the statement is coded in such a way that no branch is taken. This helps ensure what gets simulated matches the functionality of what is synthesized.

 

[fragnen]

The priority and unique keywords before a SystemVerilog case statement do not change the execution behavior of the case statement. However, they do provide violation errors if the statement is coded in such a way that no branch is taken. This helps ensure what gets simulated matches the functionality of what is synthesized.

Does it mean we should use both priority and full_case pragma together for a case statement where the case statement is incomplete I.e. a few branches are not taken?

 

[dave_59]

http://www.sunburst-design.com/papers/CummingsSNUG2005Israel_SystemVerilog_UniquePriority.pdf

 

[fragnen]

http://www.sunburst-design.com/papers/CummingsSNUG2005Israel_SystemVerilog_UniquePriority.pdf

According to this paper priority behaves like a full_case. That means priority makes a case statement whose all case items are not defined to behave like a full case. Is not it?

 

[fragnen]

Hello dave_59,

Can you please reply to the query asked at post number 5 in this thread? Thanks in advance.

 

[dave_59]

According to this paper priority behaves like a full_case. That means priority makes a case statement whose all case items are not defined to behave like a full case. Is not it?

The paper is misleading to say that priority modifies the behavior of the case statement for simulation. What it does is add an assertion so that if your intention was to interpret it as full_case, but you missed a case item, you would get an error and nothing gets executed. Synthesis treats a missing case item in a full_case as a don't care, and you get whatever logic it most optimal to implement.

 

[fragnen]

The paper is misleading to say that priority modifies the behavior of the case statement for simulation.

Do you want to mean that then the priority modifies the behavior of the case statement for synthesis only?

 

[dave_59]

If adding an assertion is considered "modified" behavior of the priority case, then you could consider both simulation and synthesis behaviors are modified. Priority adds an assertion for simulation, and adds full_case for synthesis.

 

[fragnen]

The final answer is now being taken as below:

Priority adds an assertion for simulation, and adds full_case for synthesis. Here Priority adds full_case for synthesis means that synthesis treats a missing case item in a full_case as a don't care, and in the synthesis log file also we see that there were missing case items for that particular case statement.

Please confirm about the correctness of the final answer.

Regards

 

[fragnen]

dave_59,

Can you please confirm about the correctness of the final answer in post no 10 in this thread?