The easiest way is to think about what would happen if there was more than one bit set (even though we avoid that in this design, the synthesis tool needs to account for all logic states). If I had implemented it like this:
Code Verilog - [expand] |
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| for (oh_index = 0; oh_index < NUM_SIGNALS; oh_index=oh_index+1)
begin
if (one_hot[oh_index])
begin
if (DIRECTION == "LSB0")
index = oh_index[INDEX_WIDTH - 1:0];
else
index = ~oh_index[INDEX_WIDTH - 1:0];
end
end
end |
It would have to encode a binary signal that corresponds to the lowest bit set to be correct. The only way to do that is with a priority encoder (which has a lot of latency). If multiple bits were set with the implementation where there is an OR gate, the outputted index would be the logical OR of indices of set bits, which is meaningless. But I don't care about that case anyway.