Hey weng,
Usually, DC will fix hold violations if you have set set_fix_hold on all clocks. If bot find out the common points in Design to fix hold violations. Few buffers inserion should solve the problem . This set can be created using what if analysis in PT and write out the information from PT and DC will use this data to correct your hold violations.
some times constraints will fool you to show the wrong hold violations. for ex, your multicycle path constraints. If you adjst path for setup and forgot to adjust MCP for hold multiplier, then you will get wrong hold violations. make sure your constraints are correct.
Good luck..
Regards,
Sam