The answer is yes for both questions. I have the all the code and synthesis scripts. Also the sims works if I change the names in the test bench to mach the netlist new signals. The problem is next time when there are some more RTL updates, the tool might decide to optimize in a different way and I don't want to constantly modify the testbench. I just want to keep those ports as they are.
I made some experiments by setting set_boundary_optimization attribute to false for the module I'm interested and it seemed to worked. Not sure yet if this will give me constant results and if is affecting in any way the QoR of the synthesis.