1.can anyone telme how to write the netlist correct for 6T FinFET SRAM inverter.
2.i have a predictive technology model (PTM) file from Predictive Technology Model (PTM) for 32nm BSIM4 model card for bulk CMOS: V0.0 and
45nm sub-circuit model for FinFET (double-gate): V0.0 [for better convergence in the simulation, you can initialize the node voltage when using PTM for FinFET]
can anyone give me the netlist and model file Tspice edf file for running the 6T FinFET SRAM inverter circuit.