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Precharge pulse in SRAM circuit

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electronics20

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Hi,
I have designed a 6T SRAM cell along with precharge circuit as depicted in attached Fig. However, I dont know what pulse is appropriate for the gate of precharge circuit (ΦB`) since precharge circuit bears the responsibility of making both BL and BLB high only before read action.
plz help. thanks a lot.


SRAM1.JPG
 
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Usually both bitlines continuously stay precharged to high; just by a read or a write operation one of them will be overwritten by a low data.
 
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