Pre and Post Increment in System Verilog

[sunidrak]

hi

Can any body please explain
Pre and post Incrment in system verilog and reason for this output



module increment;
integer i=3,z;
initial
begin
z=i++/i;
$display("i=%d,z=%d "i,z);
end
endmodule

Output
# i=4
# z=0


Regards
SUNIL

 

[dave_59]

The numerator of your expression i++/i is definitely 3, but the denominator could be 3 or 4. And 3/4 as an integer is 0.

The LRM explains this quite well. See section 11.4.2 Increment and decrement operators.

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