Dear Edrin,
The answer to your question simply is that setup and hold times determines the maximun frequency of operation for your design (if we neglect clock skew).
As you know, a D-flip flop is the most important element in digital design. We also know that data flow can be synchronous, asynchronus or by consensus. If your application works as a synchronous system, you must be sure that data will move betwen succesive stages. If you neglect setup and hold times, then you may use a frequency of operation greater than the maximum allowable frequency. So, you may lose bits resulting in errors.
I just like providing an example, try to make a simple design with pipelined adder that consists of two adders, one of them is located at the bottom left of the fpga and the other is located at the top right of the FPGA chip and a register in between them . Read the timing report carefully and decrease the "diameter" between the two adders. This example will give you the feeling how important is setup and hold times.
I hope I added something to your knowledge about clock managenent.
Best wishes,
Sameh Yassin