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PowerLineCommunication - BPSK Costas Loop

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Mad I.D.

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costas loop equations

Hello.

I'm working on a "all digital" PowerLineCommunication (PLC) project. Destination chip is Xilinx Sparan 3 FPGA.
This is my first (real) communication projekt and I'm a little stuck :(

I searched the internet for all Costas Loop information available. But most of them just provide basic information about the loop (basic equations).

My questions are :
How do I optimally design loop feedback? How should the error signal control the NCO? (I would like to see some equations if possible)
And what is the bandwidth of 2 loop filters. In BPSK, data spectrum is infinite (ideal case 010101, that is pure rectangular signal). How many harmonics should my filters pass?

Please if someone knows some literature that focuses on all digital PLL like Costas loop in more detail. Thank you very much.
 

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