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Actually the power optimization of CMOS VLSI circuits includes a lot of techniques that can be applied on different levels of abstraction throughout design flow. I think you need to start from studying the types of power dissipation in CMOS VLSI circuits. And then you can proceed with the techniques of power optimization for each type. I'll give you a brief description of power types and some of the optimization techniques. Generally, power dissipation in CMOS circuits is divided to dynamic power which is dissipated when circuit is in a working mode and static which corresponds to sleeping mode of a circuit. For optimization of a dynamic power can be applied the following techniques: clock gating, operand isolation, power gating, frequency/voltage scaling etc.. For optimization of static power the techniques that are usually applied are: multi Vth cells, body biasing etc..
So you need to do some research about power types, and optimization techniques mentioned above. Each of the optimization techniques mentioned above requires carefull consideration before application for a particular design.
POwer optimization techniques on an ASIC would be in the higher design levels.
For example Gating of Clock at the top of the hierarchy. Or partial gating of the clock locally during CLock tree synthesis. Apart from this you can go for partial enablling of the parts inside the chip for example enable the memory only when used etc. But it has its own delay issues. Apart from that most of the chips these days also have a clock switching network which would basically switch the clock to a low frequency clock to save power. Another caution is to make sure that there is no high impedance busses or outputs which are floating. This will dramatically decrease the power.