Power open during pin tapping in floorplanning

[phy_des]

hi all....

during floorplan...inspite of declaring all the pin access points of pad cells.... there is power open during pad pin tapping ...... what could be the reason

regards
aswin

 

[chetanbs]

Re: pin tapping

check for port declaration for the pads. also check if the pad pins are associated with power ports correctly

 

[phy_des]

Re: pin tapping

hi chetanbs.......

all the pins are associated with the respective nets and also the ports are declared before associating ...... the problem is the internal pins like the FP,VSS:,VDD:......... etc are not tapped to the respective nets........we can route them manually but imagine there are about 470 pad cells......and the other drc's such as spacing and shots are arising since its made up of multiple layers......

can you suggest me some other options?

regards
aswin