power on reset circuit -help!

[mickey0908]

would anyone please tell how design a power on reset circuit in the condition of vdd from 2.3 to 5.5 ,and the delayed time is 20us . thanks !!!

 

[ahmad_abdulghany]

None clear question!

Try to draw a block diagram descriping your problem, and state it more clearly..
Then, someone may understand and hints to the solution...

Best wishes,
Ahmad,

 

[IanP]

http://www.actel.com/documents/POR_Circuit_AN.pdf

Regards,
IanP

 

[mickey0908]

thanks !
The POR circuit needs delayed time 20us when the power supply added .

mickey0908.

 

[devura]

Hi

Try this IC from National. Its simple and sweet

**broken link removed**

 

[butterfish]

**broken link removed**

Regards,
IanP

this poweron have two problem:
1> it can not work if vdd rise too slowly, for this, need large R&C;
2> on the other hand, if R,C are too large, glitchs on vdd will trig RESET, means
circurt will be reset time to time;

 

[iamxo]

**broken link removed**
Regards,
IanP

this poweron have two problem:
1> it can not work if vdd rise too slowly, for this, need large R&C;
2> on the other hand, if R,C are too large, glitchs on vdd will trig RESET, means
circurt will be reset time to time;

you said so good!
but how did you know this?

 

[surianova]

**broken link removed**

Regards,
IanP

this poweron have two problem:
1> it can not work if vdd rise too slowly, for this, need large R&C;
2> on the other hand, if R,C are too large, glitchs on vdd will trig RESET, means
circurt will be reset time to time;

the glitch problem can be solved if you use internal voltage regulator to power up the POR. Your regulator must have good PSRR.

 

[butterfish]

**broken link removed**
Regards,
IanP

this poweron have two problem:
1> it can not work if vdd rise too slowly, for this, need large R&C;
2> on the other hand, if R,C are too large, glitchs on vdd will trig RESET, means
circurt will be reset time to time;

the glitch problem can be solved if you use internal voltage regulator to power up the POR. Your regulator must have good PSRR.

you are right, but I dont think this poweron is good.

Added after 2 minutes:

**broken link removed**

Regards,
IanP

this poweron have two problem:
1> it can not work if vdd rise too slowly, for this, need large R&C;
2> on the other hand, if R,C are too large, glitchs on vdd will trig RESET, means
circurt will be reset time to time;

you said so good!
but how did you know this?

it can be found by simulation.

 

[HENRY14]

Hi, I need to make "Zero standby-current power-on reset circuit".
Necessary to make the schematic, which works as follows:
If the supply voltage is smaller than 2.1 V, then the value at the
output is equal to the supply voltage, if the supply voltage is
greater than 2.1 V, then the output is connected to ground. Time
changes of supply voltage (Trise on picture) can be infinitely
large.
Here is an image

Can you advise any good circuit?
Sorry if something is unclear. English is not my native language.

 

[erikl]

If "zero standby-current" is related to the "no voltage" phase, you can use any circuit: no (supply) voltage - no current ;-) . I'd recommend a (low-power) comparator with some hysteresis.

"Zero current" during ramp-up/down or correct supply voltage isn't possible, I think. Can be done with a current consumption of less than 100nA, however. Some companies call it "zero current" anyway ;-)

 

[steadymind]

I designed one similar to ur specs but it consumes about 200nA(worst case). had a low power psuedo bandgap and comparator to detect the crossing.

i will try to get a schematic.

 

[DXNewcastle]

If I assume that the phrase "zero-standby current" refers to BOTH the no-voltage phase and to the full-voltage phase then I wonder why you don't just use a single PNP transistor with a zenner to limit its emitter voltage to the required threshold?
This will conduct only when the supply voltage is present and below the the threshold voltage.

Add a resistor between emitter and V+ (supply rail), a resistor between collector & 0v, and a resistor between base and V+ (to bias the transistor 'on' when V+ is below the threshold).
It will conduct when the supply voltage is between about 0.7volt and 0.7 volts below the zenner's voltage, conducting through the 2 resistors (on emitter and collector), these would be chosen to suit the load which would be applied across the collector resistor.

 

[E-design]

Not sure if I understand your problem fully but the general idea can be implemented around a nano power comparator like the LTC1540 from Linear Tech.
http://cds.linear.com/docs/Datasheet/1540fas.pdf

 

[HENRY14]

Sorry I did not write at once. I work in submicron cmos process with a supply voltage equal to 2.5 V.
I use Cadence IC.
The main problem is that there should be zero current consumption (no more 10nA) when the supply voltage established and I can not use band-gap reference.
There are many schematics that are simple to implement. They work at a small value of Trise (1-300 uS), but if, for example, Trise is 5 seconds, then the schematic does not work.
An example of one such scheme was given.

DXNewcastle
You are right, the phrase "zero-standby current" refers to BOTH the no-voltage phase and to the full-voltage phase.

 

[erikl]

I work in submicron cmos process with a supply voltage equal to 2.5 V.
I use Cadence IC.
The main problem is that there should be zero current consumption (no more 10nA) when the supply voltage established

Hi Henry,

if you don't need high precision, you can achieve it by using a chain of Vt-diodes with very long channels, in the order of W/L = 1:50 .. 1:100 , s. the schematic below. And you would need one insane long pMOS (W/L ≈ 1:40000).
I have used 0.25µm models:

Perhaps you can use a min. size drain-to-bulk connected pMOS instead of this terribly long T7, as described , (s. Fig. 2 , p. 1700) . You will need the Replica Bias circuit (Fig. 5 , p.1702), however.

Just try and simulate (and optimize) with your process models!