Power mosfet gate charge vs. Gate-source-voltage charateristic

[bryanurbe]

Hello To All,

Hope this message finds everyone well. I have the following question:

The Qg Vs. Vgs characteristic provided for many power MOSFETs is often limited to a peak Vgs of 10V and it is given for some assumed test conditions (i.e. Vds = 300, Id = 55A, & Ig = 10mA - please see attached datasheet for IXFN110N60P3). That being said, my questions are:

1) How should I determine my desired gate charge if I want to operate the devise at a different set of values than those assumed by the manufacturer in generating the Qg Vs. Vgs characteristic curve.

2) If I want to apply a Vgs of 15V (i.e. to achieve minimum Rds on), is it acceptable to obtain the required gate charge by extrapolating the given Qg Vs. Vgs characteristic?

Thanks in advance for any assistance you may be able to provide.

Regards,


Bryan

 

[KlausST]

Hi,

To q1: As you can see the gate charge depends on a number of parameters. Because gate charge is a imortant parameter in designing switch mode power supply, the manufacturer test this parameter in production. If one part does not meet the specifications then it is sorted out. If anybody wants to check the datasheet information, he must test the device with the same parameter as the manufacturer. So he needs all the parameters.
In general: the desired gate charge should be as low as possible to get fast swiching and therefore low swithing loss.Mind: fast switching also means high electro magnetic noise.

2) this is only one part of it. Q is the integral of current over time. In the gate charge diagram you can see three regions.
Starting at zero there is a line with about constant slope. The slope depends mainly on ciss in parallel to coss, the length depends mainly on vgth. In this region the fet is non conductive.
The second region is an about horizontal line. This depends mainly on coss, drain voltage and a bit on load current. In this region the fet gets conductive and the drain voltage is dereasing (about constantly). The decreasing voltage combined with coss forms the "miller charge". At the end oft the horizontal line the drain voltage is about at its minimum.
The third is calculated like the first region, the length depend on the Vgate - as you mentioned right.

In total the charge depends mainly on your desired application voltage and coss.
If you want to calculate the total loss of the fet:
* in the first region only gate charge
* in the second region gate charge and mainly switching current and switching time
* in the third region mainly rdson

Hope this helps
Klaus

 

[FvM]

It's quite simple. The Qgd part (Vgs plateau) in the Qg versus Vgs curve has to be scaled with switched Vds. The "excess" charge right from the plateau can be extrapolated.