sometimes, for AMP layout, we must use power or ground metal cross all the matched mos, I know the best case is not cross any gate, for if metal cross gate, there would be para cap and will impact the Vth of mos.
so there comes a problem, if I have choice, which would be better if use power/ground cross the amp? In other means, which net is more clean between power and ground?
In fact metal over matched MOS devices increase number of surface states under gate oxide and decrease device matching (sigma Vth at least).
If matching is critical you should avoid any metal over matched devices. It's not a matter of parasitic cap.
If you don't have any choice IMHO it will be better to select net with voltage closes to voltage on bulks of crossed devices. E.g. ground for NMOSes and VDD for PMOSes.
It depends on what the FETs are referred to. In general
you would like to plate them with source-connected
metal if they are operating unidirectionally.
I doubt that metal has any direct causation of surface
states but local fields will alter how they populate,
passivate or depassivate. I would be more inclined to
suspect the spacers than the "real" gate under poly.
I would be interested to see any device-physics
references for undesirable effects of field plating.
Guys, there is not just capacitive effect. To get answers for your questions I refer you to following IEEE works:
1) Microelectronic Test Structures, 1997. ICMTS 1997. Test structures for investigation of metal coverage effects on MOSFET matching
2) Electron Devices Meeting, 1996. IEDM '96., International Effects of metal coverage on MOSFET matching
3) 2007 IEEE International Conference on Microelectronic Test Structures, March 19-22, Tokyo, Japan.
Impact of Sinter Process and Metal Coverage on Transistor Mismatching and Parameter Variations in Analog CMOS Technology
There are some others works on this topic in different sources than IEEE.