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Power/Ground pad requirement for chip design!

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corgan

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chip design pads

Hi,
Is there any information or rule of thumb about how many
power/ground pad should be placed for a chip ?

Thanks in advance!
 

ymli

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number of power and ground pad -patent

It depends on your library used, I guess.
For example, I know when using a specific library, it require to insert
a pair of VDD/GND for every 8 pad, so that it can provide sufficient
current to make the chip work.
 

moorhuhn

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ground pad chip

Your question can not be answered unless you specify e.g.
technology, I/O supply level, core supply level, number of outputs, tristates, their drive strenghts, which ones have to be considered to be
simultaneusly switching outputs (SSO),number of inputs, specify which
are clock ones, analog ones (any low noise consideration ?), which package frame or better said expected inductancy, core power estimation,
allowed IR drop limit. .... There are too many things which you should know unless you are using a library provided by the vendor. They usually
have also application notes, nice tables which can be used to answer
your question. My contribution was not an answer at all, was it ? :wink:
Ooops, is supposed that you are going to do a design in CMOS, aren't you ?
 

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