Power-gating using MTCMOS in SRAM

[z3nger]

Hello all. Can someone explain to me how the SRAM cell manages to retain its data when you implement power-gating? Assuming a 6T cell architecture, once you assert sleep, the back to back inverters will have lost power..how does it retain it's value?

thanks in advance.

 

[haykp]

Actually to save the state the always-on power rail is being connected to the schematic. And retention flops are being inserted in the design.
For 6T cells, usually they are not power gating, otherwise they will loose their state.