envyh123
Newbie level 3
I have written a verilog code for a circuit (test.v) and a testbench (testd_tb.v).I use these commands for generating the power using cadence encounter RTL compiler.
I have made 3 folders. Work,RTL(where all .v files are stored), Library(which has slow_normal.lib).
In the work folder i type these commands :
2)set_attribute lib_search_path ../library
3)set_attribute hdl_search_path ../rtl
4)set attribute library slow_normal.lib
5)read {testd.v}
6)elaborate
7)synthesize -to_mapped
8)report power
The above commands help me to generate the power for the design but i am unable to get test bench specific power output.Kindly do suggest me the changes that can be made in this code.
I have made 3 folders. Work,RTL(where all .v files are stored), Library(which has slow_normal.lib).
In the work folder i type these commands :
2)set_attribute lib_search_path ../library
3)set_attribute hdl_search_path ../rtl
4)set attribute library slow_normal.lib
5)read {testd.v}
6)elaborate
7)synthesize -to_mapped
8)report power
The above commands help me to generate the power for the design but i am unable to get test bench specific power output.Kindly do suggest me the changes that can be made in this code.