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Power estimation using Cadence Encounter

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envyh123

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I have written a verilog code for a circuit (test.v) and a testbench (testd_tb.v).I use these commands for generating the power using cadence encounter RTL compiler.
I have made 3 folders. Work,RTL(where all .v files are stored), Library(which has slow_normal.lib).
In the work folder i type these commands :
1)rc -gui(to invoke the encounter tool)
2)set_attribute lib_search_path ../library
3)set_attribute hdl_search_path ../rtl
4)set attribute library slow_normal.lib
5)read {testd.v}
6)elaborate
7)synthesize -to_mapped
8)report power

The above commands help me to generate the power for the design but i am unable to get test bench specific power output.Kindly do suggest me the changes that can be made in this code.
 

jbeniston

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You need to read in a VCD generated in your sim:

read_vcd -static -vcd_module dut sim.vcd
 

envyh123

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i have tried generating a vcd file using command
$dumpfile("testd.vcd");
$dumpvars;
but i cannot find a vcd file that is generated.
I have a .gz file though.
Can you please elaborate the methods.Any useful links will also do.
Thanks you
 

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