Power Estimation or Analysis during RTL stage

[preposturous]

I am designing a RTL design which has a small processor and simple peripheral .
I have the RTL and will be writing the assembly code for the RTL.

I wanted to do a power analysis i.e. estimate the power consumption of the RTL at the architecture stage itself .

Can somebody provide me an idea about how the power estimation is done industry-wide while designing products ?

 

[YuLongHuang]

I am designing a RTL design which has a small processor and simple peripheral .
I have the RTL and will be writing the assembly code for the RTL.
I wanted to do a power analysis i.e. estimate the power consumption of the RTL at the architecture stage itself .
Can somebody provide me an idea about how the power estimation is done industry-wide while designing products ?

There are several EDA tools which can analyze the power at RTL stage.
For example, PowerArtist developed by Apache.
But I don't know whether it's effective or reliable.

 

[alexhugo]

You must do a synthesis to be able to have an accurate estimate.
This URL may help you:
**broken link removed**