For the full adder circuit realized with one 3-input XOR gate for sum, three 2-input AND gate and one 3-input OR gate the power consumed for these gates is x mW. The full adder circuit designed from two 2:1 multiplexers, one XOR/XNOR, one AND/OR gate based on the value of c input is ymW. I find that y>x. I request you to let me know if this is because the full adder circuit in traditional way has multiple instances of same logic gate consuming less power.
You can easily draw the circuit and see how many nets toggle..... Power = C*V*V....so you have to calculate the amount of cap that is charged during an input to output path....