Within the mux you have on resistance of the switches
and shunt capacitances. Input shunt cap causes loss in
the driving network's resistance. Output shunt cap loss
is across Ron. You should have minimal, but maybe not
negligible, losses through the FET gates' capacitances,
to the internal gate drivers' on resistance, to the supplies.
Through-losses will be across Ron through the load C
(if this is CMOS logic) or perhaps also some DC losses if
driving a resistive impedance).
Of course you also have CVf current in the enable paths
if toggling.
You should try to understand the structure, draw it out
and the loss paths should become pretty evident to
inspection. Old CMOS databooks from RCA, et al have
nice detailed transistor level schematics which you
could simplify for analysis purposes, to Rs and Cs.