wireless man
Full Member level 1
Hi, everyone,
In my power amplifier design, When I place 4 transistors in parallel as output stage, it can delivery 24 dBm power.
When add more transistors in parallel (base current increased accordingly), the output power doesn't increase but decrease to 23 dBm. Why? should I need do a input matching network before the transistors ?
Is there anybody can show me the reason?
Thanks.
The simulation is performed in ADS.
In my power amplifier design, When I place 4 transistors in parallel as output stage, it can delivery 24 dBm power.
When add more transistors in parallel (base current increased accordingly), the output power doesn't increase but decrease to 23 dBm. Why? should I need do a input matching network before the transistors ?
Is there anybody can show me the reason?
Thanks.
The simulation is performed in ADS.