hamidmoallemi
Full Member level 2
Hi
I am doing my project on "implemetation of wimax FEC processor on 0.18um Cmos"
I have written codes for some of my blocks in verilog and simulated them successfully in Modelsim ,I have synthesized my verilog codes with TSMC 0.18um standard cells using "Cadence PKS_shell" and extracted synthesized verilog code ,
now I want to do post synthesize verilog simulation
but I just have the verilog code,what should I do?
can anyone help me on this
Thanks in advance
Hamid Moallemi
I am doing my project on "implemetation of wimax FEC processor on 0.18um Cmos"
I have written codes for some of my blocks in verilog and simulated them successfully in Modelsim ,I have synthesized my verilog codes with TSMC 0.18um standard cells using "Cadence PKS_shell" and extracted synthesized verilog code ,
now I want to do post synthesize verilog simulation
but I just have the verilog code,what should I do?
can anyone help me on this
Thanks in advance
Hamid Moallemi