always84
Member level 1
I'm using Design Compiler i wanto to make a post synthesis simulation , How can I do? I wanto to rebuild ma timing constraint (OPTIMIZATION CONSTRAINT) after synthesis of my top module, so I can set input/ouput delay in my sub designs and than I can try re-optimize they one by one. Is it possible? Another question is related to the interface logic model, that improve the timing analysis. If during post synthesis I create an interface logic for timing analysis , this can help me in my re-optimization?
