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Post-Synthesis simulation problem

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ireon

Junior Member level 2
Hello, I simulated correctly my system with a RTL simulation, now I'm trying to simulate the system with a post-syntehsis timing simulation in Vivado 2018.3. I correctly synthetized the system and I launched post-synthesis simulation from Flow-->Run Simulation-->Run Post-Synthesis Timing Simulation.

Vivado generates the following files:

In QuestaSim I compile the axi_vip_0_mst_stimulus_compile.do file and everyting is fine. When I try to run the simulation I get the errors in the attached image.

How can I solve the problem?

dpaul

Advanced Member level 5
I suspect there there is a problem with the generated sdf file. Now that can be due to an incomplete or poorly defined designed constraints file.
But why do you need to perform a Post-Synthesis Timing Simulation? I never do it and it is not necessary!

ireon

Junior Member level 2
I suspect there there is a problem with the generated sdf file. Now that can be due to an incomplete or poorly defined designed constraints file.
But why do you need to perform a Post-Synthesis Timing Simulation? I never do it and it is not necessary!
The post-synthesis is required for the design validation.

Super Moderator
Staff member
The post-synthesis is required for the design validation.
In the 30+ years I've been working on FPGAs I've only had to resort to post synthesis simulation twice.

Once was to verify the synthesis results were not the same as the design description. The synthesis tool had a bug and we had to migrate to a different version of the tools.

The second time was to determine why different builds of an FPGA didn't work compared to another build with only minor changes (like changing a constant). This turned out to be place and route logic synthesis breaking our design.
--- Updated ---

Since I don't run this type of simulation very often, I'm not entirely sure of the error messages that are produced under various situations.

You should check the vsim command line (or post it) as you may be applying the SDF to the wrong level of the hierarchy. The SDF should be applied to the UUT that was synthesized and the hierarchical name needs to be used on the command line.

Last edited:

ireon

Junior Member level 2
This is the command line:

vsim -t ps -novopt -sdftyp /tb_top/TOP_ADB=axi_vip_0_mst_stimulus_time_impl.sdf tb_top -do "do wave.do; run -all"

TOP_ADB is the top of my design, tb_top is the top of my testbench, that includes TOP_ADB.

Using the -sdfnoerror in the vsim command I manage to execute the simulation, but I get the following error:

# **Error: C:\Xilinx\Vivado\2018.3\data\verilog\src\unisims\GTXE2_CHANNEL.v(3483): $period( negedge TXUSRCLK:741311157 ps, :741315154 ps, 4 ns ); # ** Error: C:\Xilinx\Vivado\2018.3\data\verilog\src\unisims\GTXE2_CHANNEL.v(3483):$period( negedge TXUSRCLK:741319156 ps, :741323147 ps, 4 ns );
# ** Error: C:\Xilinx\Vivado\2018.3\data\verilog\src\unisims\GTXE2_CHANNEL.v(3484): $period( posedge TXUSRCLK2:741329147 ps, :741333141 ps, 4 ns ); # ** Error: C:\Xilinx\Vivado\2018.3\data\verilog\src\unisims\GTXE2_CHANNEL.v(3475):$period( posedge RXUSRCLK2:741329147 ps, :741333141 ps, 4 ns );

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