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Post-synthesis simulation with ModelSim

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Hi everyone!

Here is my problem : I'm trying to validate the VHDL description of a storage unit which includes 2 SRAM blocks and glue logic. SRAM models (0.13µm technology) are provided by STMicroelectronics vendor through a specific library. The unit is synthesized with Synopsys Design Compiler 2007.03. Actually, it generates a Verilog netlist and a .sdf file (v 2.1). Then, I launch a post-synthesis simulation with ModelSim 6.3g but errors occur during the netlist backannotation step (vsim-SDF-3261). More precisely, it seems that the ModelSim engine is unable to associate SRAM timings within the .sdf file and SRAM entities declaration within the Verilog netlist. Errors occur only for SRAM blocks and not for glue logic. I don't know how to resolve this problem! Thanks a lot for your help.

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