Hello Forum,
I am working on gate level simulations for generating saif file for power estimation. I am running simulations on post ICC generated netlist and sdf file(generated from prime time using spef file extracted using star rc tool). In sdf file the min::max delays corresponds to the minimum and maximum delays of that path.
I am not doing any timing closure. So I am not worried about the timing violations. Although I have 3-4 violations only, which can be fixed using eco tool.
So when I run functional simulation on the netlist using the delays in the sdf file I observe the following pattern:
Corner 1: set up time passed and hold time failed(timing reports from prime time analysis). When I run functional simulation on the netlist by selecting max delays from the sdf file of this corner, the simulation output matched the pre synthesis simulation output. But when I simulated with the min delays (I expected it to output don't cares as the design has hold violations) surprisingly the output matched the pre synthesis simulation output.
Corner 2: set up time passed hold time failed. Post synthesis simulation results matched pre synthesis simulation results for max delays, got don't cares as outputs when I selected min delays for sdf back annotation from this corner's sdf.(results are as I expected)
Corner 3: set up time failed and hold time failed. Simulation results output don't cares for both min and max delays.(results are as I expected)
I have the following questions:
1) Can I expect the design which has hold time violations but no set up violations for a particular corner to give correct outputs (doing netlist simulation) when selected max delays from the sdf file of that corner?
2) I can not understand why for corner 1, when simulated with min delays in sdf file gave correct outputs although hold timing failed for this corner.
I can simply simulate the netlist without any delays and generate toggle rates. But I wanted to know whether my understanding about sdf file and gate level simulations is correct.