Post-synth simulation problem with Nangate Library

[ebrahimi.khoy]

Hi,

When I was trying to do the post-synth simulation for a processor synthesized with Nangate library, I saw that even functional behavior is not correct. I debug the implementation and I found that the problem is in the implementation of DFFS_X1 flip-flop and more specifically in the following lines

// Delayed data/reference logic
buf(id_6, SN);
// SDF Logic
buf(SNx, SN);

`ifdef TETRAMAX
`else
ng_xbuf(SN, SNx, 1'b1);
ng_xbuf(xid_6, id_6, 1'b1);
`endif


When I comment these lines post-synthesis simulation does correctly without any mismatch. Do you know what are these lines and why they cause problem?

The complete description of DFFS_X1 is as below:

primitive \seq_DFFS_X1 (IQ, SN, nextstate, CK, NOTIFIER);
output IQ;
input SN;
input nextstate;
input CK;
input NOTIFIER;
reg IQ;

table
// SN nextstate CK NOTIFIER : @IQ : IQ
1 0 r ? : ? : 0;
? 1 r ? : ? : 1;
1 0 * ? : 0 : 0; // reduce pessimism
? 1 * ? : 1 : 1; // reduce pessimism
1 * ? ? : ? : -; // Ignore all edges on nextstate
1 ? n ? : ? : -; // Ignore non-triggering clock edge
0 ? ? ? : ? : 1; // SN activated
* ? ? ? : 1 : 1; // Cover all transitions on SN
? ? ? * : ? : x; // Any NOTIFIER change
endtable
endprimitive

module DFFS_X1 (D, SN, CK, Q, QN);
input D;
input SN;
input CK;
output Q;
output QN;
reg NOTIFIER;

`ifdef NTC
`ifdef RECREM
buf(SN_d, SN_di);
`else
buf (SN_d, SN);
`endif
\seq_DFFS_X1 (IQ, SN_d, nextstate, CK_d, NOTIFIER);
not(IQN, IQ);
buf(Q, IQ);
buf(QN, IQN);
buf(nextstate, D_d);

// Delayed data/reference logic
buf(id_8, SN_d);
// SDF Logic
buf(SNx, SN_d);

`ifdef TETRAMAX
`else
ng_xbuf(SN_d, SNx, 1'b1);
ng_xbuf(xid_8, id_8, 1'b1);
`endif
`else

\seq_DFFS_X1 (IQ, SN, nextstate, CK, NOTIFIER);
not(IQN, IQ);
buf(Q, IQ);
buf(QN, IQN);
buf(nextstate, D);

/*
// Delayed data/reference logic
buf(id_6, SN);
// SDF Logic
buf(SNx, SN);

`ifdef TETRAMAX
`else
ng_xbuf(SN, SNx, 1'b1);
ng_xbuf(xid_6, id_6, 1'b1);
`endif
*/
`endif

specify
(posedge CK => (Q +: D)) = (0.1, 0.1);
if((CK == 1'b0) && (D == 1'b0)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);
if((CK == 1'b0) && (D == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);
if((CK == 1'b1) && (D == 1'b0)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);
if((CK == 1'b1) && (D == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);
(posedge CK => (QN -: D)) = (0.1, 0.1);
if((CK == 1'b0) && (D == 1'b0)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);
if((CK == 1'b0) && (D == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);
if((CK == 1'b1) && (D == 1'b0)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);
if((CK == 1'b1) && (D == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);
`ifdef NTC
`ifdef RECREM
$recrem(posedge SN, posedge CK, 0.1, 0.1, NOTIFIER, , ,SN_di, CK_d);
`else
$hold(posedge CK, posedge SN, 0.1, NOTIFIER);
$recovery(posedge SN, posedge CK, 0.1, NOTIFIER);
`endif
$setuphold(posedge CK &&& (SN === 1'b1), negedge D, 0.1, 0.1, NOTIFIER, , ,CK_d, D_d);
$setuphold(posedge CK &&& (SN === 1'b1), posedge D, 0.1, 0.1, NOTIFIER, , ,CK_d, D_d);
$width(negedge CK &&& (SN === 1'b1), 0.1, 0, NOTIFIER);
$width(negedge SN, 0.1, 0, NOTIFIER);
$width(posedge CK &&& (SN === 1'b1), 0.1, 0, NOTIFIER);
`else
$hold(posedge CK, posedge SN, 0.1, NOTIFIER);
$recovery(posedge SN, posedge CK, 0.1, NOTIFIER);
$setuphold(posedge CK &&& (SN === 1'b1), negedge D, 0.1, 0.1, NOTIFIER);
$setuphold(posedge CK &&& (SN === 1'b1), posedge D, 0.1, 0.1, NOTIFIER);
$width(negedge CK &&& (SN === 1'b1), 0.1, 0, NOTIFIER);
$width(negedge SN, 0.1, 0, NOTIFIER);
$width(posedge CK &&& (SN === 1'b1), 0.1, 0, NOTIFIER);
`endif
endspecify

endmodule

 

[rca]

Did you means simulation with or without timing?