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Post Synopsys Synthesis Simulation Using ModelSim

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FNK

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modelsim synopsys library

Any idea how to do this?
 

niko_zhang

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modelsim timing.lib

Verilog(netlist)+sdf
 

M

mdlin

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modelsim synopsys technology library

vsim -sdfmin xxx.sdf
vsim -sdfmax xxx.sdf
 

gnomix

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modelsim sdfmax

#******************************************
# For Modeltech Simulator.
#******************************************
#VHDL

vlib work (create working library)
vlib target (create technology library)
vcom tech.vhd -work target (compiling technology library)
vcom -explicit netlist.vhd (compiling synopsys vhdl output)
vcom -explicit test_benches.vhd (compiling your test benches)
vsim -t ps -sdfmin /UUT=netilst.sdf test_benches (vsim with time=ps timing min (sdfmin/sdftyp/sdfmax) backannotation file= netlist.sdf (file writed by synopsys with command write_sdf (I'm not sure)) test_benches=architecture name of your test benches)


#Verilog
vlog -explicit netlist.v
vlog -explicit test_fixture.v
vsim -t ps -sdfmin /UUT=netilst.sdf test_fixture
 

FNK

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worst case simulation with modelsim

I got some good docs from Xilinx Site for this. Hope it will be helpful.

I have now done this type of simulation ... thanks.
 

FNK

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modelsim sdfmax

Using Model Technology ModelSim with Xilinx Foundation Series Software
 

FNK

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modelsim + synopsys library

This one is best. It explains how to compile Simprim libraries

Using ModelSim with Xilinx Alliance Software.
 

snakebites

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post synthesis is simulation

If you use Xilinx core,then core lib is also needed.
 

aadfar

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best case sdf modelsim

Is it no diffrences between VHDL and Verilog?
 

elektrom

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sdfmax

Who exactly know about the different between -sdfmin, -sdftyp & -sdfmax in ModelSim?
 

elektrom

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sdftyp modelsim

EDA_Master said:
Sorry for my stupid question? :D Who is tnx?

Hi tnx,

Do you know the different between sdfmin, sdftyp and sdfmax?
 

philewar

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modelsim worst case time delays

elektrom said:
EDA_Master said:
Sorry for my stupid question? :D Who is tnx?

Hi tnx,

Do you know the different between sdfmin, sdftyp and sdfmax?
Hi,

SDF will annotate delay to your design and delay can be described under three conditions, which are min:typ:max. Normally, min means best case, max for worst case while typ for the situation between min and max.
-sdfXXX is a switch to choose annotate which kind of delay.

How to calculate the delay depends on your library. I recommend you dig deeper in SDF format and certain kind of timing library such .lib or .tlf.

Please correct me if i miss anything.
Thx.
 

elektrom

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sdf modelsim vlog vsim

THX, :eek:
 

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