xtcx
Advanced Member level 1
- Joined
- Dec 22, 2007
- Messages
- 493
- Helped
- 65
- Reputation
- 130
- Reaction score
- 58
- Trophy points
- 1,308
- Location
- Bangalore, India
- Activity points
- 5,003
Hi friends
Just I could not understand why XST (Xilinx synthesis tool) synthesizes this piece of code and removes everything (almost everything) with some warnings saying : xxx has constant value and hence removing. The logic, is simple.
I know this is not a good way of writing an FSM using an integer as state selector. Out of my interests, I did this on purpose to see how it behaves. The behavioral simulation ran correct as expected, but in hardware all I found is nothing other than GRND driving to DL_Data and DL0_Fifo_Wr. All logics are removed.
however when I changed the next state process, when others => next_ss <= 0;
I just got my code synthesized. All I want to know is, after all covering all states, what does it have to do with completely removing hardware??..Latches were removed, but how good does that solve this case?.
Actual Code:-
Just I could not understand why XST (Xilinx synthesis tool) synthesizes this piece of code and removes everything (almost everything) with some warnings saying : xxx has constant value and hence removing. The logic, is simple.
A timer counts for some time and generates a pulse which triggers the FSM logic to write 64-bit data into FIFO by generating Fifo write signal.Once it writes all 41 QWords twice, the loop repeats
I know this is not a good way of writing an FSM using an integer as state selector. Out of my interests, I did this on purpose to see how it behaves. The behavioral simulation ran correct as expected, but in hardware all I found is nothing other than GRND driving to DL_Data and DL0_Fifo_Wr. All logics are removed.
Code:
[B]some warnings [/B]
WARNING:Xst:737 - Found 1-bit latch for signal <next_SS<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <next_SS<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <next_SS<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:1293 - FF/Latch <next_SS_0> has a constant value of 0 in block <DL_Data_Pump>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <next_SS_3> has a constant value of 0 in block <DL_Data_Pump>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <next_SS_1> has a constant value of 0 in block <DL_Data_Pump>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <DL_Data_45> (without init value) has a constant value of 0 in block <DL_Data_Pump>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <DL_Data_44> (without init value) has a constant value of 0 in block <DL_Data_Pump>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <DL_Data_43> (without init value) has a constant value of 0 in block <DL_Data_Pump>. This FF/Latch will be trimmed during the optimization process.
however when I changed the next state process, when others => next_ss <= 0;
I just got my code synthesized. All I want to know is, after all covering all states, what does it have to do with completely removing hardware??..Latches were removed, but how good does that solve this case?.
Actual Code:-
Code:
-- Target Devices: Virtex 6, 240 LXT
-- Tool versions: ISE 13.2
-- Description: This module will generate 2 DL packets and send them continuously to GTX encoder.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DL_Data_Pump is
-- generic ( timeout : integer := 500);--5187);
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
DL0_Fifo_wr : out STD_LOGIC;
DL1_Fifo_wr : out STD_LOGIC;
DL_Data : out STD_LOGIC_VECTOR (63 downto 0)
);
end DL_Data_Pump;
architecture Behavioral of DL_Data_Pump is
type array_big is array (0 to 40) of std_logic_vector(63 downto 0);
constant cluster_config_data : array_big:=( x"2324262A2A262423",
x"0018300041054104", x"0001006407800001",
x"000700c000060002", x"000500d000020064",
x"000b395f000a0001", x"0009000000080144",
x"000fc821000e0003", x"000dffff000c0001",
x"0013000000120003", x"0011ffff00100003",
x"001900d800180048", x"00179ff400140000",
x"078400030783ffff", x"0782000107813935",
x"0788fac8078795c0", x"0786000007850000",
x"078cff00078b9966", x"078a969607890000",
x"07906996078f0ff0", x"078e6666078dff00",
x"0794f0f007930ff0", x"079200000791f0f0",
x"0798000007979696", x"0796666607959966",
x"079d00e5079c00e5", x"079b6ac0079a28d8",
x"07a1038307a00000", x"079f0000079e0000",
x"07a53a0007a40000", x"07a3001007a20000",
x"07a9014407a80001", x"07a7000007a60000",
x"07ad100007ac7fff", x"07ab100007aa0066",
x"07b2000007b00000", x"07af000607ae8000",
x"0000000307b60000", x"07b5000007b40000",
x"0780000300000001",x"2A2624232324262A"
);
signal timer_cnt : integer range 0 to 65535 := 0;
signal timer_trigger,timer_enable : std_logic:='0';
signal present_SS,next_SS : integer range 0 to 15 := 0;
signal timeout : integer range 0 to 65535:=0;
signal i : integer range 0 to 63 := 0;
begin
----------------------
-- Local timer
----------------------
timer_mod : process(clk)
begin
if rising_edge(clk) then
if reset = '1' or timer_enable = '0' then
timer_cnt <= 0;
timer_trigger <= '0';
else
timer_cnt <= timer_cnt + 1;
if (timer_cnt < timeout) then
timer_trigger <= '0';
else
timer_cnt <= 0;
timer_trigger <= '1';
end if;
end if;
end if;
end process;
--------------------------------------
-- Sequential Present state process
-------------------------------------
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
DL_Data <= (others => '0');
DL0_fifo_wr <= '0';
present_SS <= 0;
i <= 0;
DL_Data <= (others => '0');
DL1_fifo_wr <= '0';
else
present_SS <= next_SS;
case present_SS is
when 0 => timer_enable <= '1'; -- Enable timer
timeout <= 5000; -- Load timeout value
when 1 => timer_enable <= '0'; -- Disable timer
i <= i + 1; -- Array counters
if (i = 0) then
DL0_fifo_wr <= '1';
DL_Data <= cluster_config_data(i);
elsif (i > 0) and (i < 41) then
DL_Data <= cluster_config_data(i);
else
DL0_fifo_wr <= '0'; -- Disable FIFO WRite
i <= 0;
end if;
when 2 => timer_enable <= '1'; -- Enable Timer
timeout <= 50; -- Load timeout value
when 3 => timer_enable <= '0'; -- Disable Timer
i <= i + 1; -- Array counters
if (i = 0) then
DL1_fifo_wr <= '1';
DL_Data <= cluster_config_data(i);
elsif (i > 0) and (i < 41) then
DL_Data <= cluster_config_data(i);
else
DL1_fifo_wr <= '0'; -- Disable FIFO WRite
i <= 0;
end if;
when others => null;
end case;
end if;
end if;
end process;
---------------------------------
-- Combo State change process
---------------------------------
process(next_ss, timer_trigger, i)
begin
case next_ss is
when 0 => if timer_trigger = '1' then
next_SS <= 1;
else
next_SS <= 0;
end if;
when 1 => if (i > 40) then
next_SS <= 2;
else
next_SS <= 1;
end if;
when 2 => if timer_trigger = '1' then
next_SS <= 3;
else
next_SS <= 2;
end if;
when 3 => if (i > 40) then
next_SS <= 0;
else
next_SS <= 3;
end if;
when others => null;
end case;
end process;
end Behavioral;