Post layout simulation

[Zarrin]

Hi everybody
I have a placed and routed design in SOC Encounter. I want to feed some test vectors to my design and extract its logical outputs. Since the logical values of primary outputs in my design are dependent on the exact delay of paths, i had to place and route my design to account for the net delays and other parasitic factors. Now the question: How can i perform a post-layout simulation of my design? Is there any way to do this in SOC Encounter itself? I mean, does SOC accept test vectors for simulation purposes? Is there any way to perform post layout simulation using ModelSim? If so, please provide me the steps required to do the job. Thanks.

 

[weetabixharry]

I would be interested to know the answer to this. Certainly, you should be able to simulate post-synthesis. I would guess that you can also simulate post-place. Hopefully, someone here can answer this.

 

[ivb1991]

I never had to do this, but according to my understanding you have to extract delays(in SDF format) from layout and annotate them to post-layout gate-level netlist, and then perform typical simulation as for pre-layout netlist. Try to search about SDF extraction and annotation for more details.

 

[Zarrin]

I never had to do this, but according to my understanding you have to extract delays(in SDF format) from layout and annotate them to post-layout gate-level netlist, and then perform typical simulation as for pre-layout netlist. Try to search about SDF extraction and annotation for more details.

Thanks for your reply. This is exactly what i need.