Post-layout simulation

[Dar89]

Hello, this is my first post, I hope this is the correct section . I've designed a D flip-flop and I've realized the layout, then, with starXCT, i've extracted parasitic and maked the post layout simulation. I have to design a very speed flip-flop to use it in a full custom design, so I'm interested to delay (time to clock and setup time). The effect of parasitic ( extracted with a RCmax methodology) is the following:
TcqLH=45.09 ps (schematic)->53 ps (post-layout simulation)
TcqHL=45.16 ps (schematic)->67.54 ps (post-layout simulation)
I don't have experience in this situations, but for me, the delay in the case of TcqHL is too high, respect to the schematic simulation. So i've indentified the capacitances responsible of that and i've incremented the W of some mosfet in the layout (without moving any interconnect), obtaining the following timing:
TcqLH=43.21 ps (schematic)->52.38 ps (post-layout simulation)
TcqHL=40.24 ps (schematic)->57.11 ps (post-layout simulation)
The percentage of parasitic on delay in the two cases is the same, but now i go a little fast. Is this degradation of timing caused by interconnect acceptable?

Thanks

 

[Junus2012]

dear Da89

I dont have long experiance in the layout design, but in general there is special rules for routing high speed IC. so you can search on it

Hello, this is my first post, I hope this is the correct section . I've designed a D flip-flop and I've realized the layout, then, with starXCT, i've extracted parasitic and maked the post layout simulation. I have to design a very speed flip-flop to use it in a full custom design, so I'm interested to delay (time to clock and setup time). The effect of parasitic ( extracted with a RCmax methodology) is the following:
TcqLH=45.09 ps (schematic)->53 ps (post-layout simulation)
TcqHL=45.16 ps (schematic)->67.54 ps (post-layout simulation)
I don't have experience in this situations, but for me, the delay in the case of TcqHL is too high, respect to the schematic simulation. So i've indentified the capacitances responsible of that and i've incremented the W of some mosfet in the layout (without moving any interconnect), obtaining the following timing:
TcqLH=43.21 ps (schematic)->52.38 ps (post-layout simulation)
TcqHL=40.24 ps (schematic)->57.11 ps (post-layout simulation)
The percentage of parasitic on delay in the two cases is the same, but now i go a little fast. Is this degradation of timing caused by interconnect acceptable?

Thanks

 

[lamoun]

Well, in high speed design the parasitics of the interconnections are one of the main contributors of postlayout delay..
You can try using more vias (less resistance hence lower RC constant) and lower resistivity / capacitance metals. For example M1 is probably much "slower" than top metal.

Also fingering the transistors has an effect on the speed of the design (this might not be modeled correctly and thus not appear in schematic simulations)
And of course mutual inductance plays an important role in such high speeds.

 

[Dar89]

I've yet fingered the transistor, now i'll try to add more vias, thanks