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post layout simulation

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terry8

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i meet a big problem

i finish the all of steps from DC & ICC,

there is no timing violation in DC & ICC

and also the pre layout simulation & DRC & LVS is correct.

when i do the post layout simulation in ncverilog

some error like this
"tsmc18.v", 21081: Timing violation in testtop.u1.core.y_reg_2_
$setuphold<hold>( posedge CK &&& (SandRandSEb == 1):93500, posedge D:93500, 1.00 : 100, 1.00 : 100 );

what it means? really confuse me long time!!

who can help me? thx
 

rca

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that's mean that the flop y_reg_2 has a hold time violation.
the violation could be true or "false".
"false" is this register is directly drive by an "asynchronous" signal (from external pad or macro), which is not synchrone with your clock. You could inactivate, in Questa, the check the hold time for all registers that are directly drive by an external signals.
true means an issue in your STA analyzis or wrong constraint (SDC). In primetime, used "report_analysis_coverage" to know how your design is timing check covered.
 

vijayatmu

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Agree with rca reply. It is also likely, the specify timing check is not conditioned properly. I have seen many such false failures in my project.
 

ljxpjpjljx

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first check with designer to see whether there are real timing violation!
 

terry8

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to rca:
i don't understand you mean exactly.

i check my design,and find the error is occur in SDFF, and D & clk & reset port connect to combinational circuit's output

so what do i check ?


to ljxpjpjljx :
how to? in post simulation ,i just in unix terminal run the verilog , it shows some timing violation error

and to see the vcd file, the output value is unknow , but why design compile & ICC tell me the timing is met
 

rca

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Hi terry8,

The verilog which modelise the flop contains some time check (hold/setup).
The sdf back attonate the verilog to indicate what are the margins and delay...
During your simulation post-layout with timing, the simulator will check that all this time check are respected, like hold time on D pin versus CLK pin.
If your design is timing clean, and the D pin is driven by an other memory element (flop or memories), the hold must not violated. A violation means, wrong timing constraint that mask the hold checks.
If the D pin is driven by an asynchronous signal, that is not "controllable" when it is asserted & de-asserted, the timing check versus the CLK pin must be ignore because, the place and route tool does not know the timing relation.

is it more clear?
 
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    terry8

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