nanavaras6284
Member level 1
I am a student working on a Digital IC design.
I have completed the design layout using SOC Encounter and generated the verilog and sdf files from the layout design.
When I tried to simulate this post-layout netlist with NCVerilog, I see Glitching noise at the output. Please refer to the attached screenshot of the glitches which occurs exactly at the rising edge or falling edge of the signals.
The Pre-layout simulation didnot show this problem.
Can some one help me what should be done to solve this issue.
I have completed the design layout using SOC Encounter and generated the verilog and sdf files from the layout design.
When I tried to simulate this post-layout netlist with NCVerilog, I see Glitching noise at the output. Please refer to the attached screenshot of the glitches which occurs exactly at the rising edge or falling edge of the signals.
The Pre-layout simulation didnot show this problem.
Can some one help me what should be done to solve this issue.