Post Layout simulation for multi-finger transistors

[Junus2012]

Hello

When there is a mosfet with more than one finger, the annotation on the schematic displays only for a single finger (not for all fingers).", this is happening only with layout exctraction simualtion.

as an example, a transistor in the schematic has ID = 100 µA and it is constructed using 2 gates and segments (multiplication factor = 2*2=4). in the post layout simulation, the measured or annotated value is 25 µA!!!. whivh means that I have to multiply it myself with 4, however, I believe that cadence are smarter than me and it must include a method to correct the reading automatechally

thank you
best regards

 

[Dominik Przyborowski]

Depends to virtuoso version, PDK and simulator.
I believe, extraction were done by QRC and you are using spectre.
Please provide above information and if you get any message in CIW about backanotation, paste it as well.

 

[Junus2012]

Dear Dominik,

I am using Cadence Virtuso 6.18-64 bit

I am receiving the attached image from the CIW

 

[Dominik Przyborowski]

Which release of virtuoso? 6.1.8 before ISR12 has some issues with this. CDNS support page about this

 

[dick_freebird]

It may be that the extraction does not
combine fingers into a single FET. This
was a problem at the last straight job I
worked, to the point that the CAD group
had one of its minions write a script to
churn a netlist and turn any number of
fully-parallel, same-geometry fingers
into a single instance in the
analog_extracted netlist.

I expect this means there was no good
Cadence-native way to get the same
result.

It might be easier to put a little square
of "resistor" marker in the drain interconnect
outboard of where all fingers merge, and
place a metal resistor in the schematic to
match, this will force the currents to be
"collected" into that probe-able element.

 

[Junus2012]

Which release of virtuoso? 6.1.8 before ISR12 has some issues with this. CDNS support page about this

I saw this link but it is referring to an internal document "A fix for this CCR is available in IC6.1.8/ICADVM18.1 ISR12, which is available on https://downloads.cadence.com." which I couln't find

--- Updated Mar 19, 2021 ---

It may be that the extraction does not
combine fingers into a single FET. This
was a problem at the last straight job I
worked, to the point that the CAD group
had one of its minions write a script to
churn a netlist and turn any number of
fully-parallel, same-geometry fingers
into a single instance in the
analog_extracted netlist.

I expect this means there was no good
Cadence-native way to get the same
result.

It might be easier to put a little square
of "resistor" marker in the drain interconnect
outboard of where all fingers merge, and
place a metal resistor in the schematic to
match, this will force the currents to be
"collected" into that probe-able element.

Yes you are right, this problem was at the old cadence, but with the new version I am using they supposed to solve it, otherwise I could also manually calculating the current values

 

[Dominik Przyborowski]

I saw this link but it is referring to an internal document "A fix for this CCR is available in IC6.1.8/ICADVM18.1 ISR12, which is available on https://downloads.cadence.com." which I couln't find

It is not reffering to any document but to software. Until you will not use 6.1.8-12 (or newer) version, the issue will not be solved.

I expect this means there was no good
Cadence-native way to get the same
result.

Basically, it is on table for more than decade. Case is, the device cdf should use proper function to calculate OPs and extractor should provide proper naming of instances.

 

[timof]

This may be a problem with a very old technology.

In new technologies / PDKs, the LVS recognizes each finger as a separate instance, with a bunch of unique instance parameters (that are layout-dependent - hence the fingers are not merged together), and LVS should match (cross-reference) multiple post-layout instances with a single schematic element.