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[SOLVED] Post Layout Simulation error

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vashistha

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Hello,
I am using hspice for post layout simulation of inverter and got an error "No dc path to ground from node 1: 4". (Node 1 is vdd).
 

Generally node0 is considered as ground and has to be mentioned in the circuit for the proper working of the circuit.If node0 is not present,it is mandatory to mention one node as ground.
 

Maybe your post-layout netlist does not map (or name)
nets the same as your schematic based testhench?
 

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