Why do you call "nch_mac" a mismatched model?
From what I know, nch_mac is a macromodel (i.e. a wrapper around a transistor model, that captures some of the parasitics).
In old nodes, like 180nm, they used straight SPICE models (like BSIM3 or BSIM4) and not macromodels.
Why do you expect to see nch_mac for this process?
Of course, you can replace model names by editing text file (DSPF) - but if these models are not present in SPICE library - you will get errors form your simulations.
- - - Updated - - -
QRC - Cadence now names it Quantus, or Quantus QRC - is extraction tool different from Assura.
- - - Updated - - -
Unfortunately, existing flows in IC design field do not allow to simulate mismatch caused by layout parasitics (which can dominate in advanced technology nodes).